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rev. b a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?analog devices, inc., 2002 ad adc80 12-bit successive-approximation integrated circuit a/d converter features true 12-bit operation: max nonlinearity 0.012% low gain t.c.: 30 ppm/ c max low power: 800 mw fast conversion time: 25 s precision 6.3 v reference for external application short-cycle capability parallel data output monolithic dac with scaling resistors for stability low chip count?igh reliability industry standard pinout ??models for 12 v supplies functional block diagram 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 bit 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 bit 6 bit 5 bit 4 bit 3 bit 2 5v analog supply digital gnd comparator in bipolar offset out 10v span in 20v span in analog gnd 5v digital supply gain adjust bit 8 bit 9 bit 10 bit 11 bit 12 (lsb) nc ?15v or ?12v ref out (6.3v) clock out status short cycle clock inhibit external clock in convert start 15v or 12v comp 12-bit sar reference clock and control circuits ad adc80 12-bit dac nc = no connect bit 1 (msb) bit 1 (msb) product description the ad adc80 is a complete 12-bit successive-approximation analog-to-digital converter that includes an internal clock, refer- ence, and comparator. its hybrid ic design uses msi digital and linear monolithic chips in conjunction with a 12-bit monolithic dac to provide modular performance and versatility with ic size, price, and reliability. important performance characteristics of the ad adc80 include a maximum linearity error at 25 c of 0.012%, max gain t.c. of 30 ppm/ c, typical power dissipation of 800 mw, and max con- version time of 25 s. monotonic operation of the feedback d/a converter guarantees no missing codes over the temperature range of C 25 c to +85 c. the design of the ad adc80 includes scaling resistors that provide analog signal ranges of 2.5 v, 5.0 v, 10 v, 0 v to 5.0 v, or 0 v to 10.0 v. the 6.3 v precision reference may be used for external applications. all digital signals are fully dtl and ttl compatible; output data is in parallel form. the ad adc80 is available in grades specified for use over the C 25 c to +85 c temperature range and is available in a 32-lead ceramic dip. product highlights 1. the ad adc80 is a complete 12-bit a/d converter. no external components are required to perform a conversion. 2. a monolithic 12-bit feedback dac is used for reduced chip count and higher reliability. 3. the internal buried zener reference is laser trimmed to 6.3 v. the reference voltage is available externally and can supply up to 1.5 ma beyond that required for the reference and bipolar offset current. 4. the scaling resistors are included on the monolithic dac for exceptional thermal tracking. 5. the ad adc80 directly replaces other devices of this type with significant increases in performance. 6. the fast conversion rate of the ad adc80 makes it an excellent choice for applications requiring high system throughput rates. 7. the short cycle and external clock options are provided for applications requiring faster conversion speeds or lower resolutions.
rev. b e2e ad adc80especifications (typical @ 25 c, 15 v, and +5 v, unless otherwise noted.) model ad adc80-12 unit resolution 12 bits analog inputs voltage ranges bipolar 2.5, 5, 10 v unipolar 0, +5, +10 v impedance (direct input) 0 to +5, 2.5 v 0 to +10, 5v 10 v digital inputs 1 convert command positive pulse 100 ns wide (min) ( ? 0 ? to ? 1 ? initiates conversion) logic loading 1 ttl load external clock 1 ttl load transfer characteristics error gain error 2 0.1 % of fsr 3 offset 2 unipolar 0.05 % of fsr bipolar 0.1 % of fsr linearity error (max) 4 0.012 % of fsr inherent quantization error 1/2 lsb differential linearity error 1/2 lsb no missing codes temperature range ? 25 to +85
rev. b ad adc80 e3e model ad adc80-12 unit power requirements rated voltages 15, +5 v range for rated accuracy 4.75 to 5.25 and 14.0 to 16.0 v z models 8 4.75 to 5.25 and 11.4 to 16.0 v supply drain +15 v +10 ma ? 15 v ? 20 ma +5 v +70 ma temperature range specification ? 25 to +85
rev. b e4e ad adc80 pin configuration 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 (lsb) nc ?15v or ?12v ref out (6.3v) clock out status short cycle clock inhibit external clock in convert start 15v or 12v 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 bit 6 bit 5 bit 4 bit 3 bit 2 5v analog supply digital gnd comparator in bipolar offset out 10v span in 20v span in analog gnd 5v digital supply gain adjust nc = no connect bit 1 (msb) bit 1 (msb) pin function descriptions pin no. mnemonic function 1 ? 6bit 6 ? bit 1 (msb) digital outputs 75 v analog supply analog positive supply (nominally 0.25 v) 8b it 1 (msb) msb s s m bs b s s s s s s s b s s ss s bsb b
rev. b t ypical performance characteristics?d adc80 ? conversion time ? s 1.00 02 linearity error ? lsb 4681012 14 16 18 20 24 26 28 0.50 0.25 8-bit 10-bit 12-bit tpc 1. linearity error vs. conversion time (normalized) conversion time ? s 1.00 02 differential linearity error ? lsb 468101214161 8202 42628 0.50 0.25 0.75 8-bit 10-bit 12-bit tpc 2. differential linearity error vs. conversion time (normalized) temperature ? c 0.3 ?25 gain drift error ? % of fsr ?0.3 ?0.2 ?0.1 0 0.1 0.2 025 7085 tpc 3. maximum gain drift error, % of fsr vs. temperature temperature ? c ?25 reference drift error ? % ?0.08 025 85 ?55 100 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 typical tpc 4. reference drift, % error vs. temperature
rev. b ? ad adc80 theory of operation on receipt of a convert start command, the ad adc80 converts the voltage at its analog input into an equivalent 12-bit binary number. this conversion is accomplished as follows: the 12-bit successive-approximation register (sar) has its 12-bit outputs connected both to the device bit output pins and to the corresponding bit inputs of the feedback dac. the analog input is successively compared to the feedback dac output, one bit at a time (msb first, lsb last). the decision to keep or reject each bit is then made at the completion of each bit comparison period, depending on the state of the comparator at that time. timing the timing diagram is shown in figure 1. receipt of a con vert start signal sets the status flag, indicating conversion in progress. this, in turn, removes the inhibit applied to the gated clock, permitting it to run through 13 cycles. all sar parallel b it and status flip-flops are initialized on the leading edge, and the gated clock inhibit signal is removed on the trailing edge of the convert start signal. at time t 0 , b 1 is reset and b 2 ? b 12 are set unconditionally. at t 1 , the bit 1 decision is made (keep) and bit 2 is unconditionally reset. at t 2 , the bit 2 decision is made (keep) and bit 3 is reset unconditionally. this sequence continues until the bit 12 (lsb) decision (keep) is made at t 12 . after a 40 ns delay period, the status flag is reset, indicating that the conversion is complete and that the parallel output data is valid. resetting the status flag restores the gated clock inhibit signal, forcing the clock output to the logic ? 0 ? state. parallel data bits become valid on the positive-going clock edge (see figure 1). incorporation of this 40 ns delay guarantees that the parallel data is valid at the logic ? l ? to ? 0 ? transition of the status flag, permitting parallel data transfer to be initi ated by the trailing edge of the status signal. t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 convert 1 start internal clock status msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 lsb ?0? ?1? ?1? ?0? ?0? ?1? ?1? ?1? ?0? ?1? ?1? ?0? note 3 conversion time 2 maximum throughput time notes 1 the convert start pulsewidth is 100ns min and must remain low during a conversion; the conversion is initiated by the "rising edge" of the convert command 2 25 s for 12 bits and 21 s for 10 bits (max) 3 msb decision 4 lsb decision 40ns prior to the status going low bit decisions note 4 figure 1. timing diagram (binary code 011001110110)
rev. b ad adc80 ? digital output data parallel data from ttl storage registers is in negative true form. parallel data output coding is complementary binary for unipolar ranges and either complementary offset binary or complementary twos complement binary, depending on whether bit 1 (pin 6) or its logical inverse bit 1 (pin 8) is used as the msb. parallel data becomes valid approxi- mately 40 ns before the status flag returns to logic ? 0, ? permitting parallel data transfer to be clocked on the ? 1 ? to ? 0 ? transition of the status flag. parallel data outputs change state on positive-going clock edges. there are 13 negative-going clock edges in the complete 12-bit conversion cycle, as shown in figure 1. the first edge shifts an invalid bit into the register, which is shifted out on the 13th negative-going clock edge. short cycle input a short cycle input, pin 21, permits the timing cycle shown in figure 1 to be terminated after any number of desired bits has been converted, permitting somewhat shorter conversion times in applications not requiring full 12-bit resolution. when 10-bit resolution is desired, pin 21 is connected to bit 11, output pin 28. the conversion cycle then terminates, and the status flag resets after the bit 10 decision (t 10 + 40 ns in timing dia- gram of figure 1). short cycle pin connections and associated maximum 12-, 10-, and 8-bit conversion times are summarized in table i. when 12-bit resolution is required, pin 21 is con- nected to 5 v (pin 9). input scaling the ad adc80 input should be scaled as close to the maximum input signal range as possible to use the maximum signal resolution of the a/d converter. connect the input signal as shown in table ii. see figure 2 for circuit details. comparator r2, 5k to sar from d/a converter 10v range 13 20v range 14 comp in 11 6.3k v ref bipolar offset analog common 12 15 r1, 5k figure 2. input scaling circuit table i. short cycle connections connect short maximum status cycle pin 21 resolution conversion flag to pin bits (% fsr) time ( s) reset 91 2 0.024 25 t 12 + 40 ns 28 10 0.100 21 t 10 + 40 ns 30 8 0.390 17 t 8 + 40 ns table ii. input scaling connections input connect connect connect signal output pin 12 pin 14 input range code to pin to signal to 10 v cob or ctc 11 input signal 14 5 v cob or ctc 11 open 13 2.5 v cob or ctc 11 pin 11 13 0 v to 5 v csb 15 pin 11 13 0 v to 10 v csb 15 open 13
rev. b ? ad adc80 offset adjustment the zero adjust circuit consists of a potentiometer connected across v s with its slider connected through a 1.8 m w resistor to comparator input pin 11 for all ranges. as shown in figure 3 the tolerance of this fixed resistor is not critical, and a carbon composition type is generally adequate. using a carbon compo- sition resistor having a ? 1200 ppm/ 11 10k to 100k +15v ?15v figure 3. offset adjustment circuit an alternate offset adjust circuit, which contributes negligible offset tempco if metal film resistors (tempco <100 ppm/ mf 180k mf 11 10k to 100k +15v ?15v 22k mf figure 4. low tempco zero adjustment circuit in either zero adjust circuit, the fixed resistor connected to pin 11 should be located close to this pin to keep the pin 11 connection runs short. comparator input pin 11 is quite sensi- tive to external noise pickup. gain adjustment the gain adjust circuit consists of a potentiometer connected across v s with its slider connected through a 10 m w resistor to the gain adjust pin 16 as shown in figure 5. gain adjust ad adc80 10m 16 10k to 100k +15v ?15v 0.01 f figure 5. gain adjustment circuit an alternate gain adjust circuit, which contributes negligible gain tempco if metal film resistors (tempco <100 ppm/ to 100k +15v ?15v 0.1 f 270k mf 6.8k 270k mf figure 6. low tempco gain adjustment circuit table iii. input voltages and code definitions binary (bin) output analog input voltage range defined as: 10 v 5 v 2.5 v 0 v to 10 v 0 v to 5 v code cob 1 cob 1 cob 1 designation or ctc 2 or ctc 2 or ctc 2 csb 3 csb 3 one least fsr 20 v 10 v 5 v 10 v 5 v significant 2 n 2 n 2 n 2 n 2 n 2 n bit (lsb) n = 8 78.13 mv 39.06 mv 19.53 mv 39.06 mv 19.53 mv n = 10 19.53 mv 9.77 mv 4.88 mv 9.77 mv 4.88 mv n = 12 4.88 mv 2.44 mv 1.22 mv 2.44 mv 1.22 mv transition values msb lsb 000 . . . . 000 4 +full scale 10 v ? 3/2 lsb 5 v ? 3/2 lsb 2.5 v ? 3/2 lsb 10 v ? 3/2 lsb 5 v ? 3/2 lsb 011 . . . . 111 midscale 0 0 0 5 v 2.5 v 111 . . . . 110 ? full scale ? 10 v + 1/2 lsb ? 5 v + 1/2 lsb ? 2.5 v + 1/2 lsb 0 v + 1/2 lsb 0 v + 1/2 lsb notes 1 cob = complementary offset binary 2 ctc = complementary twos complement ? obtained by using the complement of the most significant bit ( msb ). msb is available on pin 8. 3 csb = complementary straight binary 4 voltages given are the nominal value for transition to the code specified.
rev. b ad adc80 ? calibration external ero adj and gain adj potentiometers, connected as shown in figures 7 and 8, are used for device calibration. to prevent interaction of these two adjustments, zero is always adjusted first and then gain. zero is adjusted with the analog input near the most negative end of the analog range (0 for unipolar and ?s for bipolar input ranges). gain is ad justed with the analog input near the most positive end of the analog range. 0 to 10 v range set analog input to +1 lsb = 0.0024 v. adjust zero for digital output = 111111111110. zero is now calibrated. set analog input to +fsr ?2 lsb = 9.9952 v. adjust gain for 000000000001 digital output code. full-scale (gain) is now calibrated. for half-scale calibration check set analog input to 5.0000 v; digital output code should be 011111111111. ?0 v to +10 v range set analog input to ?.9951 v, adjust zero for 111111111110 digital output (complementary offset binary) code. set ana- log input to +9.9902 v, adjust gain for 000000000001 digital output (complementary offset binary) code. for half-scale calibration check, set analog input to 0.0000 v; digital output (complementary offset binary) code should be 011111111111. other ranges representative digital coding for 0 v to 10 v and ?0 v to +10 v ranges is given above. coding relationships and calibration points for 0 v to 5 v, ?.5 v to +2.5 v, and ? v to +5 v ranges can be found by halving the corresponding code equivalents listed for the 0 v to 10 v and ?0 v to +10 v ranges, respectively. zero and full-scale calibration can be accomplished to a preci sion of approximately 1/4 lsb using the static adjustment proce dure described above. by summing a small sine- or triangular-wave voltage with the signal applied to the analog input, the output can be cycled through each of the calibration codes of inter- est to m ore accurately determine the center (or end points) of each discrete quantization level. a detailed description of this dy namic calibration technique is presented in ?/d conversion notes,?d. sheingold, analog devices, inc., 1977, part ii, chapter 3. comp ad adc80 sar dac 1.8m ?15v +15v 10k analog input +5v +15v ?15v ?15v +15v 10k 10m 0.01 f ref 24 17 15 25 79 10 16 12 14 13 11 figure 7. analog and power connections for unipolar 0 v?0 v input range comp ad adc80 sar dac 1.8m ?15v +15v 10k analog input +5v +15v ?15v ?15v +15v 10k 10m 0.01 f ref 24 17 15 25 79 10 16 12 14 13 11 figure 8. analog and power connections for bipolar 10 v input range
rev. b ?0 ad adc80 grounding many data-acquisition components have two or more ground pins that are not connected together within the device. these grounds are usually referred to as the logic power return, analog common (analog power return), and analog signal ground. these grounds must be tied together at one point, usually at the system power-supply ground. ideally, a single solid ground is desirable. however, since current flows through the ground wires and etch stripes of the circuit cards, and since these paths have resistance and inductance, hundreds of milli- volts can be generated between the system ground point and the ground pin of the ad adc80. therefore, separate ground returns should be provided to minimize the current flow in the path from sensitive points to the system ground point, and the two device grounds should be tied together. in this way, supply currents and logic-gate return currents are not summed into the same return path as analog signals where they would cause measurement errors. each of the ad adc80 s supply terminals should be capaci- tively decoupled as close to the ad adc80 as possible. a large value capacitor such as 1 m f in parallel with a 0.1 m f capacitor is usually sufficient. analog supplies are bypassed to the analog power return pin and the logic supply is bypassed to the logic power return pin. 0.01 f 0.01 f 0.01 f analog ps +15v ?15v c 0.01 f ad583 sample and hold 0.01 f 0.01 f output reference if independent, otherwise return amplifier reference to mecca at analog ps common * signal ground ad521 inst. amp digital ps 5v c dig com ad adc80 0.01 f 17 15 25 10 9 7 analog ground * figure 9. basic grounding practice control modes the timing sequence of the ad adc80 allows the device to be easily operated in a variety of systems with different control modes. the most common control modes are illustrated in figures 10 through 12. 5v ad adc80 bit 11 short cycle clock inhibit external clock convert command 10-bit operation 12-bit operation 18 convert command 19 20 21 28 figure 10. internal clock?ormal operating mode. conversion initiated by the rising edge of the convert command. the internal clock runs only during conversion. 5v ad adc80 bit 11 short cycle clock inhibit external clock convert command 10-bit operation 19 18 digital common digital common external clock 21 20 28 12-bit operation figure 11. continuation conversion with external clock. conversion is initiated by 14th clock pulse. clock runs continuously. ad adc80 bit 11 short cycle clock inhibit external clock convert command 10-bit operation status 19 22 18 external clock 5v digital common 12-bit operation 20 21 28 convert command figure 12. continuous external clock. conversion initiated by rising edge of convert command. the convert command must be synchronized with clock.
rev. b ad adc80 ?1 outline dimensions 32-lead side brazed ceramic dip for hybrid [medium cavity] (dh-32d) dimensions shown in inches and (millimeters) 0.930 (23.62) max 0.890 (22.61) min 0.910 (23.11) max 0.870 (22.10) min 116 17 32 1.616 (41.05) max 0.280 (7.11) max 0.005 (0.13) min 0.098 (2.49) max 0.120 (3.05) min 0.020 (0.51) max 0.016 (0.41) min 0.100 (2.54) bsc 0.055 (1.40) max 0.035 (0.89) min 0.060 (1.52) max 0.040 (1.02) min 0.180 (4.57) min 0.012 (0.30) max 0.009 (0.23) min pin 1 notes 1. index area; a notch or a lead one identification mark is located adjacent to lead one 2. the minimum limit for the dimension may be 0.023" (0.58 mm) for all four corner leads only 3. the dimension shall be measured from the seating plane to the base plane 4. the basic pin spacing is 0.100" (2.54 mm) between center lines 5. applies to all four corners 6. the dimension shall be measured at the center line of the leads 7. thirty spaces see note 1 see note 4,7 see note 2 see note 6 see note 3 see note 5 see note 5
c01202??/02(b) printed in u.s.a. ?2 ad adc80 revision history location page 9/02?ata sheet changed from rev. a to rev. b. edit to figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 outline dimensions replaced . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

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